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News from the Amateur Sky Survey
News from The Amateur Sky Survey 970605
Progress continues on the Mark IV camera. We have seen "first
light" by a very loose definition. Nothing close to an image,
but we have all the proper clocks working and can see the
expected signals from the CCD amplifier.
We have backed off on the read out speed for the first units
after looking at the signals coming from the CCD. We will now
read out the 2k x 2k device in 40-50 seconds for the first
camera. But faster 16 bit ADCs are coming, and we have designed
the system to read out as fast as 2 MHz.
All the mechanics for the triplets have been designed and are
ready to go to the shop. The package is 16" x 16" x 24" and will
contain 3 ea. 2k x 2k cameras all looking at the same patch of
sky with V, R, and I filters.
We uncovered a major problem with the memory board. It forgets
after a few milliseconds. Just what one would expect. We are
doing a major redesign. Possibly we will be able to kludge it
up to work in a few weeks so we can try to get an image with the
hay-wired but working electronics.
[snip]
.....The Control
board was made to work, revised, and we already have a new board
back from the PC house which we have started to assemble. The
Scanner board is being revised to run with a 16 bit 10 us ADC.
There was just too many things that could go wrong with the fast
two step converter. The memory board is being worked on.
Next Month (June):
This month will be clean up month. We should get the revised
Scanner board out in time to have it back in June. Meanwhile we
will try to get the memory working so we can try to see an image.
We hope to start the memory board PC revisions.
We plan to completely revise the design so we can run a triplet
of cameras with one PC and one memory board.
We will also go to AAS and tell everyone what we have been doing.
Tom Droege
--------------------
The Mark IV is a stare mode 2k x 2k camera designed for general
purpose use. It features high speed read out (2-4 seconds) and
two step conversion for wide dynamic range. We plan to build a
bunch of them, so we are trying to do a finished engineering
design. Not a commercial design that we could sell without
support, but still a design that we can ship out around the world
and get operational with internet correspondence.
I will try to get one of these out monthly to keep everyone
abrest of the project. Mostly I do these for my own benefit to
force me to think about the details of the schedule and whether
there is some critical path item that I am missing.
First a little outline of how the project is organized. Such
projects have a design phase where one just thinks about it and
collects information. Then there is an implementation phase
where one executes the design. The Mark IV is in the
implementation phase. The implementation phase has a paper
design phase, a printed circuit board layout phase, and a test
phase. We are now in the test phase. Later there will be a
programming phase, but I don't like to think about that.
Last month I wrote:
We expect to complete all the PC board layouts this month
(March 1997). With normal 3 week deliveries, we will start
getting boards back from the vendor in early April. By the end
of May we should have all the boards working, and will be
starting to write test camera code in BASIC.
We did that, and all the boards are back! This for my physicist
friends that are not used to doing anything on a schedule.
There are four main boards:
The Control Board:
This board is centered around the BASIC Stamp computer. It
communicates with a computer over an RS-232 interface. It
contains a 16 bit 10us ADC and a 16 channel multiplexer that is
used to monitor operating voltages, temperatures, and the like.
It contains circuits to generate 16 pulse outputs to control
things, besides the 16 general purpose I/O lines on the stamp.
I contains an 8 way input sense multiplexer to sense single bit
conditions. It contains a stepper motor driver for the
Declination motion, and a clock and a half step stepper motor
drive for the RA drive. There is also a power amplifier and
servo for controlling the TEC cooling. There is an octal DAC
with buffer amplifiers that is used to generate the CCD clock
voltage levels.
The Scan Engine Board:
This board controls two prom controlled scan engines. One is
used for the vertical pulse generation. It has eight outputs and
is started by a pulse from the Control Board. The condition of
the output lines is determined by an 8 bit by 128K prom. It can
be clocked up to about a 14 MHz rate. This allows a different
state of the clock lines every 70 ns. A second scan engine, used
for the horizontal clocks has 16 outputs, and is again 128k long.
The way it works, the vertical engine puts out a vertical clock
sequence at the end of which it starts the horizontal engine and
pauses. The horizontal engine then puts out a sequence for a
full horizontal line, then continues the vertical engine. With
the 128K proms, we can handle comfortably CCDs to 8k x 8k or
larger.
The scan engine board also contains the dual slope double
correlated sample electronics, and gain switching amplifiers so
that we can perform two conversions per pixel to get wide dynamic
range. My guess is that this will never be used, but it will be
there if we need it.
The scan engine board contains DC-DC converter modules which get
+12 volts DC from the PC and generate +/-5, +/-15, and +20 for
the various circuits.
The Memory Board:
The memory board is built on a standard PC card. It accepts 8
bit wide data (from the Scan Engine board) and stuffs it into a
one byte by 16 meg memory on the card. It is a simple card. You
send it an byte of data and a clock and it puts it into the next
memory position. You can only reset the memory address counter
to zero.
To load the memory, the Scan Engine checks that it is empty, then
jams it full and sets a done flag.
At the PC, the done flag can cause an interrupt, which can then
be used to reset the memory address counter followed by single
byte reads. The PC must know how many bytes to read.
The Camera Head Board:
The board in the camera head receives DC voltages from the
Control card DACs and clock pulses from the Scan Engine. In
camera head switches connect to the DAC voltages to generate the
clock line signals. Note that the DG-403 switches used are the
present speed limit for the clocks. There is also a JFET buffer
amplifier for the pixel signal. Both outputs of the Ford chip
are buffered but there is only one signal line brought to the ADC
on the Scan Engine card.
The Mechanical Hardware:
The plan is to build a barn door type mount.
The Other Stuff:
The plan is to build a complete system. So there is other stuff
to think about.
Status of Construction:
The Control Board:
We have established communication with the Stamp. We send 6
ascii character strings to the stamp. The center two characters
are used as check characters. While we send full bytes, only
the low order 4 bits are used. This (I think) allows use with
almost any RS-232 device, since you can usually pick out a
sequence that does not contain anything nasty. We are using (at
the moment) 0-? which is 30-3F in hex.
We have checked out the pulse generation circuits and can
generate the 16 pulses to do various things. We have tested the
16 bit ADC and the multiplexer. We can send commands from the PC
like "read the +15 supply" and get back the current value. A
little noisier than I would like, about 1 mv rms, but everything
is still out in the open.
We have the DACs working. We can send a DAC address and a value
and read the output voltage which swings about +/- 12 volts. We
have the declination drive working. We can send a direction and
a number of steps from the PC and the motor does the right thing.
Left to test are the status sense circuits, the declination step
motor drive and clock, and the power servo for the TEC. There
are lots of blue "correction" wires. We will have to have this
board re-done at least once.
We have used the pulse output to start and stop the vertical scan
engine.
The Scan Engine Board:
Both scan engines have been wired. The vertical scan engine has
been given a few tests. Everything works as expected. Again
there are a bunch of correction wires because we mixed up inputs
and outputs on a simple AND gate. Sigh, it took forever to find
as the drawing had the pins wrong. Since both scan engines were
done from the same PC layout symbol, the second scan engine
should test quickly.
The power supply modules have been installed and the mis-wirings
repaired.
Yet to be tested is the analog circuitry and the flash ADC.
The Memory Board:
Is stuffed, but not tested?
The Camera Head Board:
Is here and fits in the camera head hardware but is otherwise
untested.
The Mechanical Hardware:
We have had pieces machined for a camera head and a simple barn
door mount. We have redesigned almost everything. (one piece
can be reused). We have decided to use a 2" square filter. The
prototype was machined with the idea we would use a 3" round
window and sit the filter on top of it. Now we plan to use a 2"
square filter as the window.
The barn door mount was a little stuffed in it's 1' cube
enclosure. We have now decided to build a triplet in a
16"x16"x24" enclosure. This gives a longer arm on the barn door
and allows finer steps (about 5") with the step motor and lead
screw that I have.
We have completed drawings for all the mechanical parts.
The Other Stuff:
We have worried a lot about grounding and shielding and how we
might operated in the field. It should only be necessary to turn
on the PC and start the program. The system then has handles to
turn on everything else, like pumps, TEC power supplies, door
openers, and the like. There are also sense inputs to make sure
that what was supposed to have happened actually happened.
We have packaged everything so that it will be very difficult to
wire it up incorrectly. This means we have used almost evey DB
connector in the series. A pain in the neck from a stocking
standpoint. My work room is full of piles of connectors.
Drawings:
We have pretty finished drawings for everything. At last count
over 50 B size drawings. We continue to update the drawings as
we make changes and are checking out the hardware using the final
drawings. Some of you will appreciate what this means for the
final quality of the documentation.
Anecdote of the Month:
Just to show what all this is about, here is what happened when
checking the serial DACs. The DACs require a 12 bit serial input
and a clock. The Stamp has a SEROUT instruction. You specify a
word to be sent, whether the most significant or least
significant bit should be sent first, and how many bits to send.
Given that a sixteen bit word was used, that 12 bits were to be
sent, and that the most significant bit was to be sent first,
guess which bits the stamp sends? No fair answering if you have
used one.
Tom Droege June 1997
From: droege@wwa.com
Subject: TASS - News From The Front
To: tass@wwa.com
[extract]
I have had the Mark IV camera head apart so many times that wires
have started falling off it. Thursday night a clock line fell off
and I had the opportunity to try to figure out why the camera was
not working when most things seemed normal. Just had to go through
and check everything.
Yesterday I carefully took things apart and cleaned up all the
connections, dressed the wiring, and set out to put the camera
permanently together. I wan un-hurried, and working carefully so as
to get the camera in shape to take sky pictures. I was so careful
and un-hurried that I plugged in Chip 17-0-0 90 degrees from it's
proper position. Sigh! 180 degrees would have done no damage, but
17-0-0 is now in that great silicon valley in the sky.
I am now testing with 14-0-0. The 0-0 0-1 ect. reffers to the quadrant
of the wafer that the chip came from. One thing I learned was the
chips were pretty much alike. I am still not using the chips that
are supposed to be the best.
I have tried to compare MPP with NMPP modes. I see very little difference
in the saturation level. That is when I expose the chip (through a lens)
so that some areas are saturated. Possibly 65,000 e- in NMPP mode and
55,000 e- in MPP mode. This led me to wonder if I was really running in
MPP mode. So I have just done a dark current test. I clear the chip
several times and note the dark level. Then I wait 3 minutes and look again
noting the dark level.
Temperature Mode Dark Current
-25 C NMPP 80 e-/sec
-34 C NMPP 21 e-/sec
-25 C MPP <10 e-/sec
The above were taken with three minute pauses between clears. I am doing a
longer run while typing this to try to get a better measure in MPP mode.
Tom Droege
[end extract]