A COMPLETELY BORING DESCRIPTION OF THE MARK III ELECTRONICS DRAWINGS

Tom Droege <droege@wwa.com> 960430

INTRODUCTION

This note will describe the drawings for the TASS Mark III telescope electronics. There are two groups of drawings. There are seven "A" sized drawings for the Control card and 10 drawings for the Data card.

First some disclaimers. I don't particularly like breaking up a design into so many pieces. But I don't have a "D" size plotter in my basement, so I am stuck. In such a situation I would normally make a key drawing for each of the groups. I just haven't gotten around to it. There are some peculiarities due to my desire to keep the design to one group of 4 I/O addresses. If I were to do it over again, I would use more addresses and simplify the logic. The write up below is given in excruciating detail, but probably still not enough if you want to actually decode some particular bits. You often just have to try bit combinations. Most of you will not want to read this document but only refer to a particular section when you have a problem. CAUTION Do not read beyond this point unless in need of a deep sleep.

There are a number of jumpers indicated on the various drawings which allow me to get the polarity right. ;^) They also allow the design to be used with some other CCD chips.

The drawings are numbered in the lower right corner as PAGE 1 OF 7 etc., for the Control Card, and PAGE 1 OF 10 for the Data Card. Thus it is easy to tell which set a particular drawing comes from. The lower left corner has a drawing name, as HSHIFT for the first Data Card drawing. I will refer to the drawings by these names and page numbers.

Some drawing conventions. A label like -THATS ME indicates that the signal is active low. A double line enclosing a label like 

_________
BDATA
---------
indicates a data bus. In this case on Data Card drawing (PC-1) an 8 bit data bus. As usual a bubble means active low. Not much else that is not obvious. I try to be consistent and number register bits from 0 (low order) to 7 (high order).

Note about the drawings.

THE CONTROL CARD

This card is a 3/4 size IBM PC compatible ISA card. The Data Card lives in an AT style slot in a standard PC. The second connector is not used but does prevent plugging a card in backwards during the checkout phase. ;^)

*PC-1 (1 OF 7)*

(GIF 60KB) This drawing contains the address decoding for the Control Card. Jumpers allow selection of addresses starting at 200H and 300H. As shipped, the jumpers select H300, H301, H302, and H303. When the 688 chip senses the selected address, it activates the 155 chip to produce the selected I/O pulses. It also pulses a one shot on the card to blink a red LED. This we have found to be very useful for diagnostics. We recommend that you leave the cover off the PC so that this LED can be observed when first attempting operation, or while working on new I/O software. This is a re-triggerable one shot, so more frequent triggering than its' few tenths of a second time will result in continuous on of the "Thats Me" LED.

The Data Card lives in an AT style slot in a standard PC. The second connector is not used but does prevent plugging a card in backwards during the checkout phase.

Selection of the card also activates a second one shot connected to the wait line. This slows down the I/O pulses to allow use of long cables.

The I/O pulses have the following functions:

*REG-2 (2 OF 7)*

(GIF 60KB) This drawing of the Control Card contains the DAC and clock control register. This is loaded by an OUT (2). The 5 high order bits control the loading of the DAC registers. Bits 6 and 7 select the DAC channel to load in the DAC725, bits 3,4,and 5 select which DAC register is loaded. See the programming examples in TASS1C.BAS and TASSBCD2.BAS for bit combinations that work.

This drawing also contains the pulse and multiplexer control register. It is loaded by an OUT (0). The bits have the following meaning.

A third register on this drawing is the auxiliary register. This information is available on an external connector for user defined purpose. It is loaded by LD AUX which is derived from OUT (1) on drawing CLOCK-1.

*REG-3 (3 OF 7)*

(GIF 45KB) Contains three input multiplexers. INP (0) reads data on the bus coming from the Data Card ADC.

INP (0) Reads status of the READY line to the Data Card. It also reads the position of 4 jumper wires that are meant to indicate the model of a tass card. If the Base Address is set at H200, then Basic will recognize this address as the GAME port interrupt. On can thus write programs with a pseudo interrupt in Basic.

INP (2) Reads a byte from the auxiliary I/O connector. This pulse is also available on this connector.

*DAC-1 (4 OF 7)*

(GIF 36KB) This drawing contains only the DAC725. This is a Burr-Brown dual 16 bit DAC. Best to look at the data sheet for details of operation.

*CLOCK-1 (5 OF 7)*

(GIF 47KB) A key item on this drawing is the READY signal. This comes from the Data Card and announces that the current operation is complete. It is connected to the STRIG input of the INP (1) 244 bus driver. One senses or interrupts on this line to notice that current operation is complete. Sorry, we did not design in the interrupt stuff, so you have to poll. Basic will do this for you. (Heh! Heh!)

This drawing contains the VCO clock. The frequency of the clock is controlled by the DAC0 channel. About a 7/1 range is available. Some values on the DAC will cause the PLL to hang or to be at a limit. Positive DAC loads from 5000 or so to 30,000 are in the useful range. Negative values or positive values near zero are not allowed though they do no damage. Start with values of 8,000 to 15,000. The clock is counted down by a 14 stage 4020 chip. The last 7 stages are selected by an 8/1 4512 data selector. This provides a range of 64/1. The VCO control provides and additional factor of about 7 for a total avail range of about 500/1. If the clock bus has a value of between 1 and 7, one of the seven ranges are selected and trigger the 123 one shot to provide vertical transfer pulses to the CCD. If the clock bus is set to zero, then the VCO is disconnected from the vertical transfer process, and vertical transfers can be performed under program control buy an INP (3).

Also on this drawing is logic that determines whether an OUT (1) generates (under control of bit 7 of the OUT (0) register) a pulse at the Data Card or a LD AUX pulse.

*MSC-1 (7 OF 7)

(GIF 42KB) This drawing shows the connector pin assignments.

*MSC-2 (6 OF 7)*

(GIF 28KB) This drawing shows the wiring for the power supply on the Control Card that turns +12 into +/- 15.

THE DATA CARD.

This card lives in the bottom of the camera enclosure. It is roughly 3"x10". This card contains the ADC and the analog circuitry. It communicates with the data card through a standard M-F DB-25 cable with pin to pin wiring. High power for the thermoelectric coolers is brought in through separate binding posts.

Many operations to the Data Card automatically reset READY. The return of READY then announces that the operation has completed. Examples of this are vertical shift, horizontal shift and start the ADC, and start the ADC only.

*HSHIFT (1 OF 10)*

(GIF 47KB) A horizontal shift is generated by an OUT (1) with suitable bits loaded into the OUT (0) register. See discussion for the drawing ANA- 1 (3 OF 10). This triggers two one shots. One generates the horizontal shift pulses through two operational amplifiers. Suitable gain and an offset potentiometer allow setting the shift levels to swing between -4 and +6 volts.

A second generates the phase reset pulse to clear the charge from the CCD cell. This is again level shifted by a medium speed op amp to provide the reset signal swing between -2 and +3 volts.

The BEFORE signal measures the reset state of the cell as one of the double correlated samples. The value is held at the end of the BEFORE pulse. Note that all three cameras are sampled at once. One item is automatically digitized by the timing chain at drawing START (4 Of 10). It is assumed that one will leave the multiplexer connected to one of the camera channels so this is efficient.

*VXFER (2 OF 10)*

(GIF 56KB) The KAF-0400 requires two spaced pulses on the phase V1 line and a pulse between them on the phase V2 line. These drive lines are a high capacitance load and require more current than is available from a common op amp.

The pulses are generated by a string of three one shots and an OR gate. Gain and level shifting are provided by op amps with offset pots to provide the -4 to +6 volt levels. A bipolar driver is made from transistors to provide the high current required. The loop is closed around the driver to the op amp to provide a stable clock drive signal.

*ANA-1 (3 OF 10)*

(GIF 47KB) This is a critical drawing to understand how various operations can be performed.

This leaves us with the problem of how to just reset READY. We want to do this after the VCO has caused a vertical shift. I do it by reseting the auxiliary control flip flop. I can always set it again if I want it set.

This drawing also contains the multiplexer for the analog signals into the ADC. I note here a drawing error. The division of the +/-5 is by 1/3, so the signal into the multiplexer should be labeled +5 x 1/3. Note that the voltages are a useful indication that the power supplies are healthy. The +/-5 is derived from the +/-15 which in turn is derived from the computer +12. So if these numbers match those when they card was set up and checked out, then the power is probably healthy. It is good to check the value from time to time. The channel is selected by an OUT(0) with the selection in bits 3,4, and 5.

*START (4 of 10)*

(GIF 42KB) The ROW SHIFT signal besides generating the signals on HSHIFT (1 OF 10) also initiates AFTER, the second of the double correlated samples. This signal is twice the length of the BEFORE signal and tracks the cell voltage after the charge has been shifted into the output buffer. As with the BEFORE signal, the sample is held at the end of the AFTER signal. Again note that all three cameras are sampled at the same time. At the end of AFTER, another one shot is triggered to determine a settling time, then a one shot generates a signal to start the ADC.

The 4071 OR gate on this page allow a path to start the ADC without a horizontal shift.

*COOL-3 (5 OF 10)*

(GIF 36KB) This is the drawing for the analog control loop for the thermo electric coolers. DAC channel 1 is the temperature command channel. Note that this circuitry is not included in serial #0. The command DAC value is compared to the feedback from the thermister in the first op amp (IC13 pins 5,6,7). The difference is connected to the integrating amplifier (IC13 pins 1,2,3). This integrated signal drive a buffer which drives an emitter follower (improperly drawn, this is a PNP transistor with the emitter up to the TECs) which in turn drives three thermoelectric coolers in series, one for each camera. The center camera contains the thermister. While not ideal - one thermister controls three cameras - we think most things that change the temperature of the CCD will act pretty equally on all three cameras. For example, ambient temperature and water temperature.

Servo fans will note the simple explanation for the circuit above. We have compensated the loop with some overshoot for fast response. The design is far from optimum. If I wanted to set it up right, I would take some data and run it through the FFT to find the transfer function between the TEC current and the thermister. For thermal circuits the time constant can be quite long. One recent design I worked on had the main pole at 13 micro hertz.

*ANA-2 (6 OF 10)*

(GIF 46KB) This drawing contains the ADC and its buffer amplifier. The ADC is pretty conventional. There is a gain of 4 in the buffer amplifier. The lead between the buffer amplifier and the pin 1 input of the ADC is kept as short as possible. Conversion is triggered by the DOIT signal that is generated on (4 OF 10). The end of conversion triggers the one shot which sets the READY flip flop. Note that READY is also set by the end of the vertical transfer.

*CCD-0 (7 OF 10)

(GIF 39KB) This is the double correlated sample circuit. The output amplifier of the KAF-0400 has the recommended 2K to ground. The signal level here is about +9 volts. It is buffered by a JFET source follower, then coupled to ground by a large (10 uf) capacitor and a 10M resistor. This large time constant and the double correlated sample scheme minimize any possible charge up effects as we scan the horizontal row. We start with both switches closed and the sample and hold capacitors track the signal from the buffer amplifier. The first phase of the row shift resets the output to the zero level. We wait a while for settling after the phase reset pulse, then open the IC18 BEFORE switch. The charge is now shifted out to the output buffer amplifier. After another suitable settling time, the IC17 AFTER switch is opened. The signal is now the difference between the BEFORE and AFTER samples. The two amplifiers IC12 buffer the charge stored on the 1 nf hold capacitors. Note that we use polyproplyene capacitors which have relatively low dielectric absorption. This prevents large signals from appearing as "ghosts" later as the capacitors "remember" their old charge value. The OPA404 amplifiers used here are relatively fast and have quite low leakage, +/- 4 pa.

The difference of the buffer amplifiers is taken in a difference amplifier which is offset to place the dark value of the CCD near - full scale.

*CCD-1 (8 OF 10)*

(GIF 39KB)

*CCD-2 (9 OF 10)*

(GIF 39KB) These drawings duplicate the function of CCD-0 with the different pin numbers of the remaining two channels.

*MSC-1 (10 OF 10)*

(GIF 37KB) This drawing shows the control cable pin assignments. It also shows the regulators that generate +/- 5 volts from the +/- 15 volts on the control cable.
Drawing Note: The drawings were produced on Tom's pen plotter and then scanned at 200 dpi (similar resolution to a FAX), and converted to GIF files. This makes the drawing large on most brousers, but any attempt to scan at less resolution made lines drop out. They do look good when printed on paper however. Mosaic printed the drawings fine on a single sheet of paper each, but Netscape tiled the output on six sheets. If you are unable print successfully, send e-mail and I will snail-mail hardcopies.

Last updated 960506. If you have trouble using this document or suggestions to make it more useful contact me:

Ron Wickersham / < rjw@crl.com>