This note describes a simple interface. The ECP (Enhanced Capabilities Port) Forward Command cycle is used to start the scan. The ECP Reverse Data Cycle is used to transfer the data from the Mark IV to the PC.
The circuits required will be built on a small printed circuit board that lays flat on the ADC Board and plugs into the present DB-25 output cable connector. The output DB-25 cable will plug into a socket on this board. This remote end of this cable will now plug into an ECP parallel port at the PC instead of the present Memory Board.
It is assumed that the PC has sent the appropriate commands through the serial port to the Stamp to make an exposure. This note covers the procedure to scan the CCD image and transfer it to memory.
The PC first sets up the block transfer location and does whatever other bookkeeping that is required.
The process is started by the PC sending a ECP Forward Command to the Mark IV. To do this, the PC follows the sequence shown in Figure 1. Not shown on the diagram is nReverseRequest. This would be high for a forward operation. The first step is to place the control byte on the data lines. Since nReverseRequest high disables the data line driver at the Mark IV end (Figure 3) , the two data ends will not fight each other. The PC now lowers the HostClock.
Figure 2. Logic to Interface the Forward Command Cycle
At the Mark IV end (Figure 2), lowering the HostClock starts a 74123 time delay. This delay is to allow the cable to settle. This is planned to be 1-2 microseconds. This should allow quite long cables. At the end of the delay, the 7474 flip flop is set causing the PeriphAck to go high. At the PC end, the parallel port notices the PeriphAck high and raises the HostClk. The HostClk high resets the 7474. This completes the Command Cycle.
The AND of data on the data lines, the 7474 being set, and the HostAck being low allow control pulses to appear at the -RS- and -Start Scan- AND gate outputs. The timing appears to be OK for both of these operations to take place at the same time. If timing turns out to be a problem these operations can be performed by separate Command Cycle operations.
The pulse -RS- (our convention is that a - before and after a signal name means NOT) resets the FIFO so that the input and output registers have the same address. This causes the FIFO to lower the -EF- (Not Empty Flag). A low means that it is not not empty.
The -Start Scan- signal is sent to the Scanner card. This will require that a connector be soldered onto the Scanner card. This is the only patch that will be required. The scanner now starts operation. Some number of microseconds pass before the first data is available to start loading the FIFO. The present PROM code performs both vertical and horizontal scans over the covered pixels. I will have to check the details, but it it possibly a few
Figure 3. Waveforms For The Reverse Command Cycle
milliseconds before the first data is available.
During this time it is assumed that the PC turns the bus around and sets up to receive data by the ECP Reverse Data Cycle. Part of this process is to set nReverseRequest low (Figure 3). This causes the logic (Figure 4) to return nAckReverse after two cable delays. This signal connects the FIFO output to the data bus.
Figure 4. Logic for the ECP Reverse Data Cycle
Eventually the first byte arrives at the FIFO from the Scanner and the ADC card. When the -Cable Clock- strobes the data into the FIFO, the input and output address registers are now different. This causes the -EF- (Not Empty Flag) to go low. This triggers the 123 (Figure 3) to generate a time delay. At the end of this delay the 7474 is set causing the PeriphClk to go low.
When the PC sees the PeriphClk low, it responds by raising HostAck. This arrives two cable delays after the 7474 was set plus the PC responset time.
This is inverted and used to clear the 7474. This in turn raises PeriphClk. When the PC sees PeriphClk move high, it strobes the data into the PC FIFO. At the Mark IV end, HostAck high advances the FIFO read pointer.
The 123 delay is triggered either by the -EF-flag going high (as on the arrival of the first byte from the Mark IV) or by the negative edge of the HostAck while the FIFO is not empty.
The FIFO will hold 40 milliseconds of data. The normal mode of operation is that the PC unloads the FIFO faster than the Mark IV loads it. This means -EF- will often halt PC unload operations. These are then resumed when the -EF- going high triggers the 123 causing the transmission of a PeriphClk to start the next byte transfer to the PC.
The process continues until the last byte is removed from the FIFO. At this point, no more PeriphClks are generated. The process should also stop when the PC collects the expected number of bytes from the Mark IV.
A write up of the signals on the ECP is included as Table I.
